1. Field of the Invention
The present invention relates, generally, to automatic test equipment (ATE) and, in one embodiment, to a method for providing high speed test vectors to a device under test (DUT) at the speed of the DUT.
2. Description of Related Art
The general speed of present day semiconductor memories is considerably slower than the speed of computational logic such as microprocessors. For example, a number of microprocessors are currently available at clock rates above 2 GHz (500 ps clock periods), while the read/write cycle time of the fastest static random access memory (SRAM) is about 2 ns and the read/write cycle time of dynamic random access memory (DRAM) is about 4 to 5 ns. Even specialized structures such as the Rambus® DRAM only provides data rates up to 800 MHz (although the specifications for the next generation Rambus® DRAM are 1 GHz). Thus, even with the fastest memory chips available today, the speed difference between memory and computational logic such as microprocessors creates a bottleneck on how fast a system can work.
To overcome memory latency, conventional computer systems pre-fetch anticipated instructions and operands (data expected to be used in subsequent computations) from system memory and store this anticipated data in multiple levels of on-chip instruction cache and data cache memories. For example, a Pentium® microprocessor uses two levels of cache (level-1 and level-2) to store the anticipated pre-fetch data. A portion of the anticipated data (generally referred to herein as a page) upon which a computation may be performed is stored in the data cache memory. While the central processing unit (CPU) performs the computation, data (instructions and operands) for the next anticipated computation (the next page) is fetched and stored in the cache memory. Thus, memory latency in data access is avoided for the system. This approach works in a majority of cases. However, once in awhile, anticipation on next operation becomes invalid. (By definition, the pre-fetching of anticipated data is a guess, and every once in awhile a wrong guess is made.) Subsequently, anticipated pre-fetched data in the cache becomes invalid. This is generally known as a page miss. Computation stalls when a page miss occurs, because the CPU has to wait until valid data is fetched from the memory.
Multi-threading computation overcomes page-miss limitations to a large extent. In multi-threading computation, the CPU performs multiple computations simultaneously (each computation is called as a thread). When a page-miss occurs on one computation (one thread), that computation stalls but other computations (other threads) continue and thus, the CPU remains active.
Although in principle, ATE systems are computer systems and a majority of computations follow the same principles as other computer systems, ATE systems are saddled with additional operational constraints. One constraint is due to the sequential vector-driven nature of ATE systems. To test an integrated circuit (IC), test patterns (test vectors) for that IC are stored in the pattern memory of the ATE. The pattern memory is equivalent to system memory of a computer system. However, instead of fetching a page, only one vector is fetched at a time (per cycle). This vector is applied to the DUT, a response from the DUT is obtained and compared with the expected value, and a pass/fail determination is made.
If at-speed testing (testing at the maximum rated speed of the device) is desired, a GHz DUT requires that the pin electronics of the ATE system apply patterns to the DUT at the same GHz rate. While the ATE clock and CPU can operate at the same GHz rate, as noted above the pattern memory cannot provide patterns at the same rate, which limits the test application rate. The previously described method of pre-fetching anticipated test vectors and storing them in cache is not applicable because a fixed stream of vectors is needed at the speed of DUT, one vector at a time, and the latency for accessing one vector either from pattern memory or from cache is the same for the ATE pin electronics. This limitation is unique to ATE systems, and becomes critical when DUT frequencies are on the order of GHz.
The preceding paragraphs demonstrate that at-speed testing of high speed DUTs is facilitated by presenting test vectors at the speed of the DUT operating frequency. A solution has not been previously available to overcome the latency of pattern memory in the ATE systems. Therefore, a need exists for a method that provides test vectors to a DUT at the speed of the DUT while overcoming the limitation imposed by memory latency.